CAP_数字捕获_实时仿真

CAP Code Module for IO3xx FPGA I/O modules

At its core the CAP (Capture) FPGA code module contains a 32-bit deep counter clocked at 33MHz and the CAP control logic. This FPGA code module requires one digital I/O line (Input) set as an input.

The CAP FPGA code module can be implemented on all
IO3xx series configurable FPGA I/O modules.

By 连接ing physical pulse trains to the input line of your selected IO3xx I/O module the CAP FPGA code module allows you to measure:

 

• pulse durations
• period durations
• PWM duty-cycles

Functional description



The xPC Target driver block coming with the CAP FPGA code module allows you to define whether your measure at the Start and Stop events shall begin at the low-to-high (Up) or the high-to-low (Down) transition.

At the Start event the counter starts to count up from 0 and stops at the defined Stop event (next low-to-high or high-to-low transition). The counter value is then latched into an output register which can then be read by the xPC Target driver block and the counter is reset to 0 for the next Start-Stop events.

Depending on the Start and Stop events defined the measured counter value represents the following pulse train durations or periods:

 

• A: Duration of High pulse (when Start=Up and Stop=Down)
• B: Duration of Low pulse (when Start=Down and Stop=Up)
• C: Period between Low-to-High transitions (when Start=Up and Stop=Up)
• D: Period between High-to-Low transitions (when Start=Down and Stop=Down)

Specifications
Minimal measurable duration: 2 x 1/33e6[MHz] = 60.61[ns]
Maximal measurable duration: (2^32-1) x 1/33e6[MHz] = 130.15[s]
Signal resolution: 1/33e6[MHz] or 30.03[ns]

参数资料:

CAP_数字捕获_实时仿真CAP,数字捕获,实时仿真