At its core the QAD (Quadrature Decoding) FPGA Code Module contains a 32-bit deep counter clocked at 33MHz and the QAD control logic. This code module requires three digital I/O lines (A, B and C/Index) set as input. Together, lines A, B, and C/Index form a channel. Such functionality is typically used for quadrature decoding for incremental encoder sensors.

The QAD FPGA code module can be implemented on all IO3xx series configurable FPGA I/O modules.

As an alternative you might also want to consider the use of the IO401 providing six 32-bit counters individually selectable for the use with absolute (SSI) or incremental encoder sensors (quarature decoding).

Key features of the QAD FPGA Code Module

The quadrature decoding FPGA Code Module analysis two 90 degrees shifted signal inputs from incremental encoders sensors to determine rotation direction and position.

Functional description

The two signals A and B in the below graph represent typical waveforms of such inputs. Signal C/Index represents the end of each complete cycle:

Depending on your required data, the QAD code module allows you to set the following parameters:

Quadrature modes:

Ø         1x: Counter increments at each rising edge event of signal A

Ø         2x: Counter increments at each rising or falling edge event of signal A

Ø         4x: Counter increments at each rising or falling edge event of signal A and B

Actions on Index (C)

You can define the following counter settings whenever C/Index is High (end of cycle):

l         Reset on index: Counter is cleared

l         Reload on index: Counter is reset with your selected init value

l         Latch on index: Stores the counter value into the output register

l         Index reference mode: Resets the counter to zero when the C/Index signal of the encoder is high for the first time. After this initial high C/Index signal, the QAD code module will ignore the C/Index signal and switch to 'ignore index input' mode.

l         Ignore index input: no action

Counting modes

l         Cycling counter: defines a counter range of -2^31 to 2^31 - 1

l         Divide-by-N: defines a counter range of - Steps per revolution to + Steps per revolution - 1. Each time the counter reaches the selected minimum or maximum Steps per revolution value, the counter is reset.

l         Single Cycle: Counting stops when a defined counting value is met. To start counting again, a reset is required.

Steps per revolution

The number of steps can be freely configured based on your hardware specifications. Typical values are powers of two (1024, 2048, 4096, …).

Specifications

10[MHz] maximum A/B input frequency