IXXAT offers an OpenCore+ variant for the integration into the Altera development environment. The IEEE 1588 FPGA IP can be used for evaluation purpose directly on an evaluation board for the period of 4 hours. Then, using the OpenCore+ implementation of Altera, the IP is held on reset and a restart is required. The MegaCore for integration into the Altera SOPC Builder (Quartus 8.1) is available as download and enables the quick and easy demonstration of the IEEE 1588 technology on Altera's FPGAs.

Content:

• IEEE 1588 FPGA IP to generate 1588 time stamps and to set-up the clock in hardware
• Including HAL device driver for Altera Nios II
• Including manual with description of the IP, registers and drivers
• Support of time stamping of IPv4, IPv6 and 802.3 PTP messages
• Including simple demo application

For evaluation purpose or portation support, a minimal demo is available, which reads the Rx time stamps and displays them via terminal application. A 1588 protocol stack is not part of the download, since this has to be implemented according to the used device.


The latest version of the IEEE 1588 FPGA IP MegaCore OpenCore+ demo can be found in the following. Access data is required for the download, which you can request here:
Access data

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