SPI Protocol Support
To communicate with serial peripheral interfaces speedgoat can implement SPI FPGA code modules providing SPI protocol and controller functionality on any of the configurable FPGA-based IO3xx series I/O modules.
The SPI bus as defined by Motorola only defines the basic interface functionality between the SPI master and the SPI slave, but doesn't come with protocol functionality.
Basic SPI Interface Functionality
- Control signals: Slave select (SS) and Serial Clock (SCLK)
- Data channels: Master Out Slave In (MOSI) and Master In Slave Out (MISO)
Once the slave is selected data is sent in full duplex mode using the MOSI and MISO data channels. Data lenght is typically a multiple of 8-bits, but it's basically possible to implement any desired lenght.
SPI FPGA Code Module - Key features
This code module, if implemented on an FPGA chip of a 3xx series I/O module installed in a speedgoat real-time target machine, provides you with an on-chip slave controller, two register banks, and a ADS8344 protocol (analog converter from Texas Instruments) allowing you to communicate between Simulink/xPC Target and your device with a serial peripheral interface (SPI master).
SPI is typically used to talk to a variety of sensors (temperature, pressure, ..), control devices, or orther communication protocol.
Given the lack of standardization speedgoat can implement a broad range of SPI functionality based on your exact needs and devices.
FPGA-based IO3xx series I/O modules
Each FPGA-based I/O module includes a Xilinx FPGA chip to implement and execute functionality which typically can't be met by fixed-functionality I/O modules and to achieve highest cycle-rate inner control loop implementations. The wide range of tranceiver types supported by the 3xx I/O modules allow you to 连接 your design with your hardware.
Key functionality provided by the FPGA I/O modules
- Digital pulse train generation and capture implementations for:
PWM, Capture, Quadrature Decoding, …
- Event-based interrupt, trigger, and inversion support
- Inter-system, -sensor/actuator, and -chip protocols (SPI, I2C, …)
- Generic digital inputs and outputs
- Analog I/O with lowest latency and/or special synchronization schemes
- Highest cycle-rate algorithmic implementations of system designs in combination with above functionality for very fast inner control loops
There is no need for you to deal with FPGA programming unless you decide to implement FPGA functionality on your own using speedgoat's FPGA engineering kits or 其他 tools.
Because FPGAs run at much higher 'speeds' than software-based designs they are also ideal to implement and co-execute very fast algorithmic subsystems on the configurable FPGA I/O module together with the upper level 'slower' dynamics on a software-based system (CPU) to further 增加
sample rates. Configurable FPGA-based I/O modules are therefore oftentimes an excellent alternative to 其他 'fast' DSP or Microcontroller based subsystems.
Overview FPGA-based I/O modules
| I/O module |
FPGA chip |
# logic cells |
Standard I/O lines |
| IO301 |
Xilinx Virtex-II |
7k |
64 TTL |
| IO302 |
Xilinx Virtex-II |
7k |
32 RS422 |
| IO303 |
Xilinx Virtex-II |
7k |
16 TTL and 24 RS422 |
| IO304 |
Xilinx Virtex-II |
7k |
32 LVDS |
| IO311 |
Xilinx Virtex-II |
24k |
64 TTL |
| IO312 |
Xilinx Virtex-II |
24k |
32 RS422 |
| IO313 |
Xilinx Virtex-II |
24k |
16 TTL and 24 RS422 |
| IO314 |
Xilinx Virtex-II |
24k |
32 LVDS |
| I/O module |
FPGA chip |
# logic cells |
Standard I/O lines |
Auxiliary I/O lines
(basic module) |
|
| IO322 |
Xilinx Virtex-4 |
41k |
30 RS485 |
56 LVCMOS plus 4 LVDS or 32 LVDS |
| IO323 |
Xilinx Virtex-4 |
41k |
16 TTL and 22 RS485 |
56 LVCMOS plus 4 LVDS or 32 LVDS |
| IO324 |
Xilinx Virtex-4 |
41k |
30 LVDS |
56 LVCMOS plus 4 LVDS or 32 LVDS |
| IO325 |
Xilinx Virtex-4 |
41k |
2 16-bit 105MHz A/D signals |
56 LVCMOS plus 4 LVDS or 32 LVDS |
By default (in price included) speedgoat implements the following set of FPGA Code Modules for the IO301-IO324: 3 x PWM, 3 x CAP, 3 x QAD, 1 x Interrupt, and 1 x Inversors. The remaining I/O lines provide support for generic digital inputs or outputs.
Other configuration as well as FPGA-based protocols or algorithmic designs can be implemented on request.
Use Cases
A frequent use case of configurable FPGA-based I/O modules is the provision of generic and more special pulse train functionality such as PWM, capture, quadrature decoding, and generic digital I/O. This functionality is available to engineers either as an option configured by speedgoat or for advanced users as configurable code modules.
The majority of configurable FPGA I/O modules provide digital I/O lines, but speedgoat also covers configurable FPGA I/O modules with analog frontends providing very fast A/D and D/A I/O together with digital I/O e.g to form high speed inner current control loop for motion control applications.
FPGA implementation services
speedgoat designs FPGA code modules and implements algorithmic subsystems to a broad range of configurable FPGA I/O modules with Virtex Xilinx chip according to your requirements.
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